1. Field of the Invention
The present invention generally relates to graphics processing and more specifically to a system and method for managing divergent threads in a single-instruction, multiple-data (“SIMD”) architecture by using control instructions to set up thread processing target addresses for synchronization, breaks, and returns.
2. Description of the Related Art
Current graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.
To further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process in parallel as much graphics data as possible throughout the different parts of the graphics pipeline. Graphics processors with SIMD (single-instruction multiple-data) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMD architecture, the same instruction is executed in parallel to process multiple data inputs. Whereas, in a MIMD architecture (multiple-instruction multiple-data), multiple different instructions may be executed in parallel to process multiple data inputs.
A SIMD architecture has inherent processing efficiencies since each instruction is executed synchronously to process the multiple data inputs. Conventional SIMD architectures follow a single flow of control for all threads in the group of execution threads. Therefore, execution threads in a group of threads that is executed synchronously are not able to branch differently (independently) when executing a break or return instruction, so the use of conditional break and return instructions is limited. Conditional break and return instructions in which threads may branch independently are used for advanced control flow in order to improve processing efficiency. In particular, threads that execute a break or return may complete processing earlier than threads that do not execute the break or return. Furthermore, it is desirable to synchronize threads that have diverged during the execution of conditional instructions so that those threads are executed in parallel.
Accordingly, what is needed in the art is branch processing for systems with SIMD architectures that allows for thread divergence and synchronization and the execution of conditional breaks and returns.